Voltage Set-up Problem on Embedded Systems with Multiple Voltages

Dynamic voltage scaling (DVS), arguably the most effective energy reduction technique, can be enabled by having multiple voltages physically implemented on the chip and allowing the operating system to decide which voltage to use at run-time. Indeed, this is predicted as the future low-power system by International Technology Roadmap for Semiconductors (ITRS). There still exist many important unsolved problems on how to reduce the system's dynamic and/or total power by DVS. One of such problems, which we refer to as the voltage set-up problem, is "how many levels and at which values should voltages be implemented for the system to achieve the maximum energy saving". It challenges whether DVS technique's full potential in energy saving can be reached on multiple-voltage systems. In this paper, (1) we derive analytical solutions for dual-voltage system. (2) For the general case that does not have analytic solutions, we develop efficient numerical methods that can take the overhead of voltage switch and leakage into account. (3) We demonstrate how to apply the proposed algorithms on system design. (4) Interestingly, the experimental results, on both real life DSP applications and random created applications, suggest that multiple-voltage DVS systems with only a couple levels of voltages, when set up properly, can be very close to DVS technique's full potential in energy saving. Parts of this report were published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 7, pp. 869-872, July 2005

Providing QoS with Reduced Energy Consumption via Real-Time Voltage Scaling on Embedded Systems

Low energy consumption has emerged as one of the most important design objectives for many modern embedded systems, particularly the battery-operated PDAs. For some soft real-time applications such as multimedia applications, occasional deadline misses can be tolerated. How to leverage this feature to save more energy while still meeting the user required quality of service (QoS) is the research topic this thesis focuses on. We have proposed a new probabilistic design methodology, a set of energy reduction techniques for single and multiple processor systems by using dynamic voltage scaling (DVS), the practical solutions to voltage set-up problem for multiple voltage DVS system, and a new QoS metric. Most present design space exploration techniques, which are based on application's worst case execution time, often lead to over-designing systems. We have proposed the probabilistic design methodology for soft real-time embedded systems by using detailed execution time information in order to reduce the system resources while delivering the user required QoS probabilistically. One important phase in the probabilistic design methodology is the offline/online resource management. As an example, we have proposed a set of energy reduction techniques by employing DVS techniques to exploit the slacks arising from the tolerance to deadline misses for single and multiple processor systems while meeting the user required completion ratio statistically. Multiple-voltage DVS system is predicted as the future low-power system by International Technology Roadmap for Semiconductors (ITRS). In order to find the best way to employ DVS, we have formulated the voltage set-up problem and provided its practical solutions that seek the most energy efficient voltage setting for the design of multiple-voltage DVS systems. We have also presented a case study in designing energy-efficient dual voltage soft real-time system with (m, k)-firm deadline guarantee. Although completion ratio is widely used as a QoS metric, it can only be applied to the applications with independent tasks. We have proposed a new QoS metric that differentiates firm and soft deadlines and considers the task dependency as well. Based on this new metric, we have developed a set of online scheduling algorithms that enhance quality of presentation (QoP) significantly, particularly for overloaded systems

QoP-Driven Scheduling for MPEG Video Decoding

MPEG video decoding algorithm has been embedded into many consumer electronic products. In this paper, we demonstrate that the completion ratio (CR) does not represent well the quality of presentation (QoP) of MPEG video. We then propose a new QoP metric, which 1) is based on frame completion ratio but 2) differentiates firm and soft deadlines and also 3) considers the frame dependency. We show that, on a set of simulated MPEG movies, the proposed QoP metric measures the QoP of the movies much better than the completion ratio. We then present a set of online scheduling algorithms that enhance QoP significantly, particularly for overloaded systems

A New Quality of Service Metric for Hard/Soft Real-Time Applications

Real-time applications often have mixed hard and soft deadlines, can be preempted subject to the cost of context switching or the restart of computation, and have various data dependency. The simple but widely used task completion ratio, as the Quality of Service (QoS) metric, does not capture these characteristics and can not reflect user perceived QoS well. In this paper, we propose a new quantitative QoS metric, which is based on task completion ratio but differentiates hard and soft deadlines and models data dependency as well. Basically, it assigns different weights to hard and soft deadline tasks, penalizes late soft task completion, and measures the tasks affected by any dropped tasks. We apply popular online schedulers, such as EDF (earliest deadline first), FCFS (first come first serve), and LETF (least execution time first), on a set of simulated MPEG movies at the frame level and for each application compare the new QoS measurement, traditional completion ratio with the “real” completion ratio which considers the number of correctly decoded frames and has been mapped to the user perceived QoS well. Experimental results show that our proposed QoS metric can reflect real life QoS much better than the traditional one

QOS-DRIVEN SCHEDULING FOR MULTIMEDIA APPLICATIONS

Multimedia applications have intrinsic quality of service (QoS) requirements that may not be captured by the simple traditional completion ratio model. We have proposed a new quantitative QoS metric based on task completion ratio while differentiating firm and soft deadlines and taking data dependency into consideration. Using the decoding of MPEG movies as an example, we have shown that the proposed QoS metric is much better than completion ratio in measuring the quality of presentation (QoP) of the movies. Based on the new QoS metric, we present a set of new online algorithms that outperform popular scheduling algorithms (such as EDF, FCFS, and LETF) and enhance QoP significantly, particularly when the system is overloaded. All the proposed online algorithms have low computation overhead and can be easily integrated into real-time operating systems to improve multimedia embedded system’s performance and/or to save system resources

A New Approach towards Solving the Location Discovery Problem in Wireless Sensor Networks

Location discovery in wireless sensor network (WSN) is the process that sensor nodes collaborate to determine the position for unknown sensor nodes. Anchors, sensors that know their locations, are expensive but are required to be deployed into the WSN to solve this problem. Thus it is desirable to minimize the number of anchors for this purpose. In this paper, we propose an anchor deployment scheme and a novel bilateration locationing algorithm to achieve this goal. The basic idea of anchor deployment method is to have three anchors deployed as a group, and locate sensors around them expansively. The novelty of our bilateration algorithm is that it in general requires only two neighbor sensors to determine a node's location. Comparing with the state-of-the-art location discovery approaches, our algorithm gives location estimation with high accuracy, low communication cost and very small anchor percentage. We conduct theoretical analysis about location estimation error and extensive simulation shows that our algorithm can derive sensor location within 4% location error and much less communication cost compared with other algorithms. UMIACS-TR-2003-11

Dual-Processor Design of Energy Efficient Fault-Tolerant System

A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the comple- tion of the primary copy. If there is no fault, the sec- ondary processor terminates its execution. Otherwise, should the fault occur, the second processor continues and completes the application before its deadline. In this paper, we study the energy efficiency of such dual- processor system. Specifically, we first derive an opti- mal static voltage scaling policy for single periodic task. We then extend it to multiple periodic tasks based on worst case execution time (WCET) analysis. Finally, we discuss how to further reduce system’s energy con- sumption at run time by taking advantage of the actual execution time which is less than the WCET. Simula- tion on real-life benchmark applications shows that our technique can save up to 80% energy while still provid- ing fault tolerance

Dual-Processor Design of Energy Efficient Fault-Tolerant System ∗

A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the completion of the primary copy. If there is no fault, the secondary processor terminates its execution. Otherwise, should the fault occur, the second processor continues and completes the application before its deadline. In this paper, we study the energy efficiency of such dualprocessor system. Specifically, we first derive an optimal static voltage scaling policy for single periodic task. We then extend it to multiple periodic tasks based on worst case execution time (WCET) analysis. Finally, we discuss how to further reduce system’s energy consumption at run time by taking advantage of the actual execution time which is less than the WCET. Simulation on real-life benchmark applications shows that our technique can save up to 80 % energy while still providing fault tolerance.

Approaching the Maximum Energy Saving on Embedded Systems with Multiple Voltages

Dynamic voltage scaling (DVS) is arguably the most effective energy reduction technique. The multiple-voltage DVS systems, which can operate only at pre-determined discrete voltages, are practical and have been well studied. However, one important unsolved problem is how many levels and at which values should voltages be implemented on a multiple-voltage DVS system to achieve the maximum energy saving. We refer this as the voltage set-up problem. In this paper, (1) we derive analytical solutions for dual-voltage system. (2) For the general case that does not have analytic solutions, we develop efficient numerical methods. (3) We demonstrate how to apply the proposed algorithms on system design. (4) Interestingly, the experimental results suggest that the multiple-voltage DVS system, when the voltages are set up properly, can reach DVS technique’s full potential in energy saving. Specifically, on the design of an ad hoc applicationspecific system and the design of the MPEG video encoder, we find that the best single-voltage systems consume 150 % and 20% more energy than the tight theoretical lower bounds, respectively. However, our approach gives dual-, 3-, and 4-voltage DVS system settings that are only 17.6%, 4.9%, and 2.6 % for the ad hoc system, and 4.0%, 1.1%, and 0.2 % for the MPEG video encoder, over the same lower bounds. 1